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When the device is shipped from Atmel, the most significant page of the memory array may not
be erased. In other words, the contents of the last page may not be filled with FFH.
2. Pin Configurations and Packages
Table 2-1.
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
Figure 2-1.
Pin Configurations
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page Write Protect Pin
Chip Reset
Ready/Busy
TSOP Top View Type 1
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 2-2.
CASON – Top View through Package
Figure 2-3.
8-SOIC
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
Figure 2-4.
28-SOIC (1)
Figure 2-5.
CBGA Top View
through Package
GND
1
28
VCC
NC
2
27
NC
1
2
3
NC
CS
3
4
26
25
NC
WP
SCK
5
24
RESET
A
SI
SO
NC
6
7
8
23
22
21
RDY/BUSY
NC
NC
B
C
SCK
NC
GND
NC
VCC
NC
NC
9
10
20
19
NC
NC
D
CS RDY/BSY WP
NC
NC
NC
11
12
13
18
17
16
NC
NC
NC
E
SO
NC
SI
NC
RESET
NC
NC
14
15
NC
Note:
1. The next generation DataFlash devices will not be
offered in 28-SOIC package, therefore, this pack-
age is not recommended for new designs.
2
AT45DB041B
3443D–DFLSH–2/08
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